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general description the max1215 is a monolithic, 12-bit, 250msps analog-to-digital converter (adc) optimized for outstanding dynamic performance at high-if frequencies up to 300mhz. the product operates with conversion rates up to 250msps while consuming only 975mw. at 250msps and an input frequency up to 250mhz, the max1215 achieves a spurious-free dynamic range (sfdr) of 72.4dbc. its excellent signal-to-noise ratio (snr) of 66db at 10mhz remains flat (within 2db) for input tones up to 300mhz. this adc yields an excellent low noise floor of -67.5dbfs, which makes it ideal for wideband applications such as cable-head end receivers and power-amplifier predistortion in cellular base-station transceivers. the max1215 requires a single 1.8v supply. the analog input is designed for either differential or single-ended operation and can be ac- or dc-coupled. the adc also features a selectable on-chip divide-by-2 clock circuit, which allows the user to apply clock frequencies as high as 340mhz. this helps to reduce the phase noise of the input clock source. a low-voltage differential signal (lvds) sampling clock is recommended for best perfor- mance. the converter? digital outputs are lvds com- patible and the data format can be selected to be either two? complement or offset binary. the max1215 is available in a 68-pin qfn package with exposed paddle (ep) and is specified over the industrial (-40? to +85?) temperature range. see the pin-compatible versions table for a complete selection of 8-bit, 10-bit, and 12-bit high-speed adcs inthis family (with or without input buffers). applications base-station power-amplifier linearizationcable-head end receivers wireless and wired broadband communication communications test equipment radar and satellite subsystems features ? 250msps conversion rate ? low noise floor of -67.5dbfs ? excellent low-noise characteristics snr = 65.5db at f in = 100mhz snr = 65db at f in = 250mhz ? excellent dynamic range sfdr = 70.7dbc at f in = 100mhz sfdr = 72.4dbc at f in = 250mhz ? 65.4db npr for f notch = 28.8mhz and a noise bandwidth of 50mhz ? single 1.8v supply ? 1006mw power dissipation at f sample = 250mhz and f in = 100mhz ? on-chip track-and-hold amplifier ? internal 1.24v-bandgap reference ? on-chip selectable divide-by-2 clock input ? lvds digital outputs with data clock output ? max1215 ev kit available max1215 1.8v, 12-bit, 250msps adc for broadband applications ________________________________________________________________ maxim integrated products 1 part temp range pin-package MAX1215EGK-D -40 c to +85 c 68 qfn-ep* max1215egk+d -40 c to +85 c 68 qfn-ep* pin-compatible versions ordering information part resolution (bits) speed grade (msps) on-chip buffer max1121 8 250 yes max1122 10 170 yes max1123 10 210 yes max1124 10 250 yes max1213 12 170 yes max1214 12 210 yes max1215 12 250 yes max1213n 12 170 no max1214n 12 210 no max1215n 12 250 no 19-3653; rev 1; 9/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed paddle. +denotes lead-free package. d = dry pack. evaluation kit available pin configuration appears at end of data sheet. downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 250mhz, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ? 1%, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av cc to agnd ..................................................... -0.3v to +2.1v ov cc to ognd .................................................... -0.3v to +2.1v av cc to ov cc ...................................................... -0.3v to +2.1v agnd to ognd ................................................... -0.3v to +0.3v inp, inn to agnd ....................................-0.3v to (av cc + 0.3v) all digital inputs to agnd........................-0.3v to (av cc + 0.3v) refio, refadj to agnd ........................-0.3v to (av cc + 0.3v) all digital outputs to ognd ....................-0.3v to (ov cc + 0.3v) continuous power dissipation (t a = +70?, multilayer board) 68-pin qfn-ep (derate 41.7mw/? above +70?) ...........................................................3333mw/? operating temperature range ...........................-40? to +85? junction temperature .....................................................+150? storage temperature range ............................-60? to +150? maximum current into any pin............................................50ma lead temperature (soldering,10s) ..................................+300? parameter symbol conditions min typ max units dc accuracy resolution 12 bits integral nonlinearity (note 2) inl f in = 10mhz, t a = +25 c- 2 0.85 +2 lsb differential nonlinearity (note 2) dnl t a = +25 c, no missing codes -1 0.5 +1 lsb transfer curve offset v os t a = +25 c (note 2) -3.5 +3.5 mv offset temperature drift 40 ?/ c analog inputs (inp, inn) full-scale input voltage range v fs t a = +25 c (note 2) 1320 1454 1590 mv p-p full-scale range temperaturedrift 130 ppm/ c common-mode input range v cm internally self-biased 1.365 ?.15 v input capacitance c in 2.5 pf differential input resistance r in 3.0 4.2 6.3 k full-power analog bandwidth fpbw 700 mhz reference (refio, refadj) reference output voltage v refio t a = +25 c, refadj = agnd 1.18 1.23 1.30 v reference temperature drift 90 ppm/ c refadj input high voltage v refadj used to disable the internal reference av cc - 0.3 v sampling characteristics maximum sampling rate f sample 250 mhz minimum sampling rate f sample 20 mhz clock duty cycle set by clock-management circuit 40 to 60 % aperture delay t ad figures 4, 11 620 ps aperture jitter t aj figure 11 0.2 ps rms downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications _______________________________________________________________________________________ 3 electrical characteristics (continued)(av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 250mhz, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ? 1%, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units clock inputs (clkp, clkn) differential clock input amplitude (note 3) 200 500 mv p-p clock input common-modevoltage range internally self-biased 1.15 ?.25 v clock differential inputresistance r clk 11 ?5% k clock differential inputcapacitance c clk 5p f dynamic characteristics (at -1dbfs) f in = 10mhz, t a +25 c 63.5 66 f in = 100mhz, t a +25 c 63.4 65.5 f in = 200mhz 65.5 signal-to-noiseratio snr f in = 250mhz 65 db f in = 10mhz, t a +25 c 63.5 65.8 f in = 100mhz, t a +25 c 62 64.3 f in = 200mhz 63.2 signal-to-noiseand distortion sinad f in = 250mhz 64.2 db f in = 10mhz, t a +25 c7 0 8 4 f in = 100mhz, t a +25 c 67 70.7 f in = 200mhz 67.1 spurious-freedynamic range sfdr f in = 250mhz 72.4 dbc f in = 10mhz, t a +25 c -87 -70 f in = 100mhz, t a +25 c -70.7 -67 f in = 200mhz -67.1 worst harmonics(hd2 or hd3) f in = 250mhz -72.4 dbc two-tone intermodulationdistortion ttimd f in1 = 99mhz at -7dbfs, f in2 = 101mhz at -7dbfs -79 dbc noise-power ratio npr f notch = 28.8mhz 1mhz, noise bw = 50mhz, a in = -9.1dbfs 65.4 db lvds digital outputs (d0p/n?11p/n, orp/n) differential output voltage |v od |r l = 100 1% 250 400 mv output offset voltage ov os r l = 100 1% 1.125 1.310 v downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications 4 _______________________________________________________________________________________ electrical characteristics (continued)(av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 250mhz, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 ? 1%, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units lvcmos digital inputs (clkdiv, t /b) digital input-voltage low v il 0.2 x av cc v digital input-voltage high v ih 0.8 x av cc v timing characteristics clk-to-data propagation delay t pdl figure 4 1.75 ns clk-to-dclk propagation delay t cpdl figure 4 3.87 ns dclk-to-data propagation delay t pdl - t cpdl figure 4 (note 3) 1.66 2.12 2.48 ns lvds output rise time t rise 20% to 80%, c l = 5pf 460 ps lvds output fall time t fall 20% to 80%, c l = 5pf 460 ps output data pipeline delay t latency figure 4 11 clock cycles power requirements analog supply voltage range av cc 1.70 1.80 1.90 v digital supply voltage range ov cc 1.70 1.80 1.90 v analog supply current i avcc f in = 100mhz 495 555 ma digital supply current i ovcc f in = 100mhz 64 75 ma analog power dissipation p diss f in = 100mhz 1006 1134 mw offset 1.8 mv/v power-supply rejection ratio(note 3) psrr gain 1.5 %fs/v note 1: +25? guaranteed by production test, <+25? guaranteed by design and characterization. note 2: static linearity and offset parameters are based on the end-point fit method. the full-scale range (fsr) is defined as 4095 xslope of the line. note 3: parameter guaranteed by design and characterization: t a = t min to t max . note 4: psrr is measured with both analog and digital supplies connected to the same potential. downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications _______________________________________________________________________________________ 5 -110 -90 -100 -60-70 -80 -50 -40 -20 -10-30 0 0 20 40 60 80 100 120 fft plot (8192-point data record) max1215toc01 analog input frequency (mhz) amplitude (dbfs) hd3 f sample = 249.99936mhzf in = 12.78683mhz a in = -1.008dbfs snr = 66.5dbsinad = 66.2db thd = -80.4dbc sfdr = 83.3dbc hd2 = -83.3dbc hd3 = -88.4dbc hd2 -110 -90 -100 -60-70 -80 -50 -40 -20 -10-30 0 0 20 40 60 80 100 120 fft plot (8192-point data record) max1215toc02 analog input frequency (mhz) amplitude (dbfs) f sample = 249.99936mhzf in = 65.03279mhz a in = -1.083dbfs snr = 66.7dbsinad = 65.6db thd = -72dbc sfdr = 73.7dbc hd2 = -82dbc hd3 = -73.7dbc hd3 hd2 -110 -90 -100 -60-70 -80 -50 -40 -20 -10-30 0 0 20 40 60 80 100 120 fft plot (8192-point data record) max1215toc03 analog input frequency (mhz) amplitude (dbfs) f sample = 249.99936mhzf in = 199.24876mhz a in = -1.018dbfs snr = 65.5dbsinad = 63.2db thd = -67dbc sfdr = 67.1dbc hd2 = -89.1dbc hd3 = -67.1dbc hd3 hd2 -110 -90 -100 -60-70 -80 -50 -40 -20 -10-30 0 0 20 40 60 80 100 120 fft plot (8192-point data record) max1215toc04 analog input frequency (mhz) amplitude (dbfs) hd3 f sample = 249.99936mhzf in = 248.62607mhz a in = -1.059dbfs snr = 65dbsinad = 64.2db thd = -71.5dbc sfdr = 72.4dbc hd2 = -82.1dbc hd3 = -72.4dbc hd2 f in -110 -90 -100 -60-70 -80 -50 -40 -20 -10-30 0 0 20 40 60 80 100 120 two-tone imd plot (8192-point data record) max1215toc05 analog input frequency (mhz) amplitude (db) f in1 2f in2 - f in1 2f in1 - f in2 f in2 f sample = 249.99936mhz f in1 = 99.21239mhz f in2 = 101.1044775mhz a in1 = a in2 = -7dbfs imd = -79dbc snr/sinad vs. analog input frequency (f sample = 249.99936mhz, a in = -1dbfs) max1215 toc06 f in (mhz) snr/sinad (db) 250 200 150 100 50 58 61 64 67 7055 0 300 snr sinad sfdr vs. analog input frequency (f sample = 249.99936mhz, a in = -1dbfs) max1215 toc07 f in (mhz) sfdr (dbc) 250 200 150 100 50 50 60 70 80 9040 55 65 75 8545 03 0 0 hd2/hd3 vs. analog input frequency (f sample = 249.99936mhz, a in = -1dbfs) max1215 toc08 f in (mhz) hd2/hd3 (dbc) 250 200 150 100 50 -95 -90 -80 -70-85 -75 -65 -60 -100 03 0 0 hd3 hd2 snr/sinad vs. analog input amplitude (f sample = 249.99936mhz, f in = 65.03279mhz) max1215 toc09 analog input amplitude (dbfs) snr/sinad (db) -5 -15 -25 -35 -45 -10 -20 -30 -40 -50 20 30 5040 60 7010 -55 0 snr sinad typical operating characteristics (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 250mhz, a in = -1dbfs; see each toc for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 , t a = +25?.) downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications 6 _______________________________________________________________________________________ typical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 250mhz, a in = -1dbfs; see each toc for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 , t a = +25?.) sfdr vs. analog input amplitude (f sample = 249.99936mhz, f in = 65.03279mhz) max1215 toc10 analog input amplitude (dbfs) sfdr (dbc) -5 -15 -25 -35 -45 -10 -20 -30 -40 -50 40 50 7060 80 9030 -55 0 hd2/hd3 vs. analog input amplitude (f sample = 249.99936mhz, f in = 65.03279mhz) max1215 toc11 analog input amplitude (dbfs) hd2/hd3 (dbc) -5 -15 -25 -35 -45 -10 -20 -30 -40 -50 -90 -80 -60-70 -40-50 -30 -100 -55 0 hd3 hd2 snr/sinad vs. sample frequency (f in = 65mhz, a in = -1dbfs) max1215 toc12 f sample (mhz) snr/sinad (db) 150 100 50 200 61 62 6664 6863 6765 6960 02 5 0 snr sinad sfdr vs. sample frequency (f in = 65mhz, a in = -1dbfs) max1215 toc13 f sample (mhz) sfdr (dbc) 150 100 50 200 55 60 8070 65 8575 9050 02 5 0 hd2/hd3 vs. sample frequency (f in = 65mhz, a in = -1dbfs) max1215 toc14 f sample (mhz) hd2/hd3 (dbc) 150 100 50 200 -105 -100 -75-90 -95 -65-80 -70-85 -60 -110 02 5 0 hd3 hd2 total power dissipation vs. sample frequency (f in = 65mhz, a in = -1dbfs) max1215 toc15 f sample (mhz) p diss (mw) 150 100 50 200 900 920910 930 980950 940 1000 970 990960 1010 890 02 5 0 integral nonlinearity vs. digital output code max1215 toc16 digital output code inl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 f in = 13mhz differential nonlinearity vs. digital output code max1215 toc17 digital output code dnl (lsb) 3584 3072 2048 2560 1024 1536 512 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 f in = 13mhz 1 -7 10 100 1000 gain bandwidth plot (f sample = 249.99936mhz, a in = -1dbfs) -5 -6 max1215 toc18 analog input frequency (mhz) gain (db) -3 -4 -1 0 -2 differential transformer coupling downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications _______________________________________________________________________________________ 7 63 6765 7169 7573 77 snr/sinad, sfdr vs. supply voltage (f in = 65.03279mhz, a in = -1dbfs) max1215toc22 supply voltage (v) snr/sinad, sfdr (db, dbc) 1.70 1.75 1.80 1.85 1.90 snr sinad sfdr av cc = ov cc 1.2460 1.24801.2470 1.25001.2490 1.2510 1.2520 internal reference vs. supply voltage max1215toc23 supply voltage (v) v refio (v) 1.70 1.75 1.80 1.85 1.90 measured at the refio pinrefadj = av cc = ov cc 0 21 3 4 5 6 -40 10 -15 35 60 85 propagation delay times vs. temperature temperature ( c) propagation delay (ns) max1215toc24 t pdl t cpdl typical operating characteristics (continued) (av cc = ov cc = 1.8v, agnd = ognd = 0, f sample = 250mhz, a in = -1dbfs; see each toc for detailed information on test condi- tions, differential input drive, differential sine-wave clock input drive, 0.1? capacitor on refio, internal reference, digital output pins differential r l = 100 , t a = +25?.) 20 3025 4035 5045 55 6560 70 -40 -30 -25 -35 -20 -15 -10 -5 0 noise-power ratio vs. analog input power (f notch = 28.8mhz 1mhz) max1215toc25 analog input power (dbfs) npr (db) wide noise bandwidth = 50mhz -100 -80-90 -60-70 -40-50 -30 -10-20 0 01 01 5 52 0 2 5 3 04 0 35 45 50 noise-power ratio plot (wide noise bandwidth: 50mhz) max1215toc26 analog input power (mhz) npr (db) f notch = 28.8mhz npr = 65.4db 60 6362 61 64 65 66 67 68 69 70 -40 10 -15 35 60 85 snr/sinad vs. temperature (f in = 100mhz, a in = -1dbfs) temperature ( c) snr/sinad (db) max1215toc19 snr sinad 60 6664 62 68 70 72 74 76 78 80 -40 10 -15 35 60 85 sfdr vs. temperature (f in = 100mhz, a in = -1dbfs) temperature ( c) sfdr (dbc) max1215toc20 -100 -88-92 -96 -84 -80 -76 -72 -68 -64 -60 -40 10 -15 35 60 85 hd2/hd3 vs. temperature (f in = 100mhz, a in = -1dbfs) temperature ( c) hd2/hd3 (dbc) max1215toc21 hd2 hd3 downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications 8 _______________________________________________________________________________________ pin description pin name function 1, 6, 11?4, 20, 25, 62, 63, 65 av cc analog supply voltage. bypass each pin with a parallel combination of 0.1? and 0.22?capacitors for best decoupling results. 2, 5, 7, 10, 15, 16, 18, 19, 21, 24, 64, 66, 67 agnd analog converter ground 3 refio reference input/output. with refadj pulled high, this i/o port allows an external reference source to be connected to the max1215. with refadj pulled low, the internal 1.23v bandgap reference is active. 4 refadj reference adjust input. refadj allows for fsr adjustments by placing a resistor or trimpotentiometer between refadj and agnd (decreases fsr) or refadj and refio (increases fsr). if refadj is connected to av cc , the internal reference can be overdriven with an external source connected to refio. if refadj is connected to agnd, the internal reference isused to determine the fsr of the data converter. 8 inp positive analog input terminal. internally self-biased to 1.365v. 9 inn negative analog input terminal. internally self-biased to 1.365v. 17 clkdiv clock divider input. this lvcmos-compatible input controls with which speed the converter?digital outputs are updated. clkdiv has an internal pulldown resistor. clkdiv = 0: adc updates digital outputs at one-half the input clock rate. clkdiv = 1: adc updates digital outputs at input clock rate. 22 clkp true clock input. this input ideally requires an lvpecl-compatible input level to maintain theconverter? excellent performance. internally self-biased to 1.15v. 23 clkn complementary clock input. this input ideally requires an lvpecl-compatible input level tomaintain the converter? excellent performance. internally self-biased to 1.15v. 26, 45, 61 ognd digital converter ground. ground connection for digital circuitry and output drivers. 27, 28, 41, 44, 60 ov cc digital supply voltage. bypass with a 0.1? capacitor for best decoupling results. 29 d0n complementary output bit 0 (lsb) 30 d0p true output bit 0 (lsb) 31 d1n complementary output bit 1 32 d1p true output bit 1 33 d2n complementary output bit 2 34 d2p true output bit 2 35 d3n complementary output bit 3 36 d3p true output bit 3 downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications _______________________________________________________________________________________ 9 pin description (continued) pin name function 37 d4n complementary output bit 4 38 d4p true output bit 4 39 d5n complementary output bit 5 40 d5p true output bit 5 42 dclkn complementary clock output. this output provides an lvds-compatible output level and canbe used to synchronize external devices to the converter clock. 43 dclkp true clock output. this output provides an lvds-compatible output level and can be used tosynchronize external devices to the converter clock. 46 d6n complementary output bit 6 47 d6p true output bit 6 48 d7n complementary output bit 7 49 d7p true output bit 7 50 d8n complementary output bit 8 51 d8p true output bit 8 52 d9n complementary output bit 9 53 d9p true output bit 9 54 d10n complementary output bit 10 55 d10p true output bit 10 56 d11n complementary output bit 11 (msb) 57 d11p true output bit 11 (msb) 58 orn complementary output for out-of-range control bit. if an out-of-range condition is detected,bit orn flags this condition by transitioning low. 59 orp true output for out-of-range control bit. if an out-of-range condition is detected, bit orp flagsthis condition by transitioning high. 68 t /b two? complement or binary output format selection. this lvcmos-compatible input controlsthe digital output format of the max1215. t /b has an internal pulldown resistor. t /b = 0: two? complement output format. t /b = 1: binary output format. ? p exposed paddle. the exposed paddle is located on the backside of the chip and must beconnected to analog ground for optimum performance. downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications 10 ______________________________________________________________________________________ detailed description theory of operation the max1215 uses a fully differential pipelined archi-tecture that allows for high-speed conversion, opti- mized accuracy, and linearity while minimizing power consumption and die size. both positive (inp) and negative/complementary ana- log input terminals (inn) are centered around a 1.365v common-mode voltage, and accept a differential ana- log input voltage swing of v fs / 4v each, resulting in a typical 1.454v p-p differential full-scale signal swing. inputs inp and inn are buffered prior to entering eacht/h stage and are sampled when the differential sam- pling clock signal transitions high. each pipeline converter stage converts its input voltage to a digital output code. at every stage, except the last, the error between the input voltage and the digital out- put code is multiplied and passed along to the next pipeline stage. digital error correction compensates for adc comparator offsets in each pipeline stage and ensures no missing codes. the result is a 12-bit parallel digital output word in user-selectable two?-complement or offset binary output formats with lvds-compatible output levels. see figure 1 for a more detailed view of the max1215 architecture. analog inputs (inp, inn) inp and inn are the fully differential inputs of themax1215. differential inputs usually feature good rejec- tion of even-order harmonics, which allows for enhanced ac performance as the signals are progress- ing through the analog stages. the max1215 analog inputs are self-biased at a 1.365v common-mode volt- age and allow a 1.454v p-p differential input voltage swing (figure 2). both inputs are self-biased through 2k resistors, resulting in a typical differential input resistance of 4k . it is recommended to drive the ana- log inputs of the max1215 in ac-coupled configurationto achieve best dynamic performance. see the transformer-coupled, differential analog input drive section for a detailed discussion of this configuration. max1215 clock- divider control clkdiv clock management inputbuffer dclkp d0p/n?11p/n dclkn 12 orp orn 2.2k 2.2k clkp clkn inp inn common-modebuffer refio refadj lvds data port reference t/h 12-bit pipeline quantizer core 2.2k inp 2.2k agnd common-modevoltage (1.365v) common-modevoltage (1.365v) inn to common mode to common mode 1.454v p-p differential fsr inp inn av cc -v fs / 4 +v fs / 4 -v fs / 4 +v fs / 4 v fs / 2 v fs / 2 figure 1. max1215 block diagram figure 2. simplified analog input architecture and allowable input voltage range downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications ______________________________________________________________________________________ 11 on-chip reference circuit the max1215 features an internal 1.23v bandgap refer- ence circuit (figure 3), which in combination with an inter- nal reference-scaling amplifier determines the fsr of the max1215. bypass refio with a 0.1? capacitor to agnd. to compensate for gain errors or increase the adc? fsr, the voltage of this bandgap reference can be indirectly adjusted by adding an external resistor (e.g., 100k trim potentiometer) between refadj and agnd or refadj and refio. see the applications information section for a detailed description of this process.to disable the internal reference, connect refadj to av cc . in this configuration, an external, stable refer- ence must be applied to refio to set the converter?full scale. to enable the internal reference, connect refadj to agnd. clock inputs (clkp, clkn) designed for a differential lvds clock input drive, it isrecommended to drive the clock inputs of the max1215 with an lvds- or lvpecl-compatible clock to achieve the best dynamic performance. the clock signal source must be a high-quality, low phase noise with fast edge rates to avoid any degradation in the noise performance of the adc. the clock inputs (clkp, clkn) are internally biased to 1.15v, accept a typical 0.5v p-p differential sig- nal swing, and are usually driven in ac-coupled configu-ration. see the differential, ac-coupled pecl- compatible clock input section for more circuit details on how to drive clkp and clkn appropriately. althoughnot recommended, the clock inputs also accept a single- ended input signal. the max1215 also features an internal clock-manage-ment circuit (duty-cycle equalizer) that ensures the clock signal applied to inputs clkp and clkn is processed to provide a 50% duty-cycle clock signal that desensitizes the performance of the converter to variations in the duty cycle of the input clock source. note that the clock duty-cycle equalizer cannot be turned off externally and requires a minimum clock fre- quency of > 20mhz to work appropriately and accord- ing to data sheet specifications. data clock outputs (dclkp, dclkn) the max1215 features a differential clock output, whichcan be used to latch the digital output data with an external latch or receiver. additionally, the clock output can be used to synchronize external devices (e.g., fpgas) to the adc. dclkp and dclkn are differential outputs with lvds-compatible voltage levels. there is a 3.87ns delay time between the rising (falling) edge of clkp (clkn) and the rising edge of dclkp (dclkn). see figure 4 for timing details. divide-by-2 clock control (clkdiv) the max1215 offers a clock control line (clkdiv),which supports the reduction of clock jitter in a system. connect clkdiv to ognd to enable the adc? internal divide-by-2 clock divider. data is now updated at one- half the adc? input clock rate. clkdiv has an internal pulldown resistor and can be left open for applications that require this divide-by-2 mode. connecting clkdiv to ov cc disables the divide-by-2 mode. max1215 referencebuffer adc full scale = reft - refb reft: top of reference ladder.refb: bottom of reference ladder. 1v av cc av cc /2 g control line to disable reference buffer reference scaling amplifier refio refadj 0.1 f 100 * *refadj maybe shorted to agnd directly reft refb figure 3. simplified reference architecture downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications 12 ______________________________________________________________________________________ system timing requirements figure 4 depicts the relationship between the clock input and output, analog input, sampling event, and data output. the max1215 samples on the rising (falling) edge of clkp (clkn). output data is valid on the next rising (falling) edge of the dclkp (dclkn) clock, but has an internal latency of 11 clock cycles. digital outputs (d0p/n?11p/n, dclkp/n, orp/n) and control input t /b digital outputs d0p/n?11p/n, dclkp/n, and orp/nare lvds compatible, and data on d0p/n?11p/n is presented in either binary or two?-complement format (table 1). the t /b control line is an lvcmos-compati- ble input, which allows the user to select the desiredoutput format. pulling t /b low outputs data in two? complement and pulling it high presents data in offsetbinary format on the 12-bit parallel bus. t /b has an internal pulldown resistor and may be left unconnectedin applications using only two?-complement output format. all lvds outputs provide a typical voltageswing of 0.325v around a common-mode voltage of roughly 1.15v, and must be terminated at the far end of each transmission line pair (true and complementary) with 100 . the lvds outputs are powered from a sep- arate power supply, which can be operated between1.7v and 1.9v. the max1215 offers an additional differential output pair (orp, orn) to flag out-of-range conditions, where out-of-range is above positive or below negative full scale. an out-of-range condition is identified with orp (orn) transitioning high (low). note: although a differential lvds output architecture reduces single-ended transients to the supply andground planes, capacitive loading on the digital out- puts should still be kept as low as possible. using lvds buffers on the digital outputs of the adc when driving larger loads may improve overall performance and reduce system-timing constraints. sampling event inn inp clkn clkp dclkp dclkn d0p/n d11p/n orp/n sampling event sampling event sampling event t cl t ch t ad t pdl t cpdl - t pdl ~ 0.4 x t sample with t sample = 1/f sample note: the adc samples on the rising edge of clkp. the rising edge of dclkp can be used to externally latch the output data. t cpdl t latency t cpdl - t pdl n n + 1 n + 8 n + 9 n - 8 n - 8 n - 7 n - 1 n + 1 n n - 7 n n + 1 figure 4. system and output timing diagram downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications ______________________________________________________________________________________ 13 applications information fsr adjustments using the internal bandgap reference the max1215 supports a full-scale adjustment range of10% (?%). to decrease the full-scale signal range, an external resistor value ranging from 13k to 1m may be added between refadj and agnd. a similarapproach can be taken to increase the adc? full-scale range (fsr). adding a variable resistor, potentiometer, or predetermined resistor value between refadj and refio increases the fsr of the data converter. figure 6a shows the two possible configurations and their impact on the overall full-scale range adjustment of the max1215. do not use resistor values of less than 13k to avoid instability of the internal gain regulation loop for the bandgap reference. see figure 6b for the results of the adjustment range for a selection of resis- tors used to trim the full-scale range of the max1215. table 1. max1215 digital output coding inp analog input voltage level inn analog input voltage level out-of-range orp (orn) binary digital output code (d11p/n?0p/n) two? complement digital output code (d11p/n?0p/n) > v cm + v fs / 4 < v cm - v fs / 4 1 (0) 1111 1111 1111(exceeds +fs, or set) 0111 1111 1111(exceeds +fs, or set) v cm + v fs / 4 v cm - v fs / 4 0 (1) 1111 1111 1111 (+fs) 0111 1111 1111 (+fs) v cm v cm 0 (1) 1000 0000 0000 or0111 1111 1111 (fs/2) 0000 0000 0000 or1111 1111 1111 (fs/2) v cm - v fs / 4 v cm + v fs / 4 0 (1) 0000 0000 0000 (-fs) 1000 0000 0000 (-fs) < v cm + v fs / 4 > v cm - v fs / 4 1 (0) 00 0000 0000 (exceeds -fs, or set) 10 0000 0000 (exceeds -fs, or set) v on ognd ov cc v op 2.2k 2.2k figure 5. simplified lvds output architecture max1215 referencebuffer adc full scale = reft - refb reft: top of reference ladder.refb: bottom of reference ladder. 1v av cc av cc /2 g control line to disable reference buffer reference- scaling amplifier refio refadj 13k to 1m 0.1 f reft refb 13k to 1m figure 6a. circuit suggestions to adjust the adc? full-scale range fs voltage vs. fs adjust resistor max1213 fig06b fs adjust resistor (k ) v fs (v) 875 750 500 625 250 375 125 1.39 1.41 1.43 1.45 1.47 1.49 1.51 1.53 1.55 1.571.37 0 1000 resistor value applied betweenrefadj and refio increases v fs resistor value applied betweenrefadj and agnd decreases v fs figure 6b. fs adjustment range vs. fs adjustment resistor downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications 14 ______________________________________________________________________________________ differential, ac-coupled, lvpecl-compatible clock input the max1215 dynamic performance depends on theuse of a very clean clock source. the phase noise floor of the clock source has a negative impact on the snr performance. spurious signals on the clock signal source also affect the adc? dynamic range. the pre- ferred method of clocking the max1215 is differentially with lvds- or lvpecl-compatible input levels. the fast data transition rates of these logic families minimize the clock input circuitry? transition uncertainty, thereby improving the snr performance. to accomplish this, a 50 reverse-terminated clock signal source with low phase noise is ac-coupled into a fast differential receiver such as the mc100lvel16d (figure 7). the receiver produces the necessary lvpecl output levels to drive the clock inputs of the data converter. transformer-coupled, differential analog input drive in general, the max1215 provides the best sfdr andthd with fully differential input signals and it is not recommended to drive the adc inputs in single-endedconfiguration. in differential input mode, even-order harmonics are usually lower since inp and inn are bal- anced, and each of the adc inputs only requires half the signal swing compared to a single-ended configu- ration. wideband rf transformers provide an excellent solution to convert a single-ended signal to a fully dif- ferential signal, required by the max1215 to reach its optimum dynamic performance. a secondary-side termination of a 1:1 transformer (e.g., mini-circuit? adt1-1wt) into two separate 24.9 ?% resistors (use tight resistor tolerances to minimizeeffects of imbalance; 0.5% would be an ideal choice) placed between top/bottom and center tap of the trans- former is recommended to maximize the adc? dynam- ic range. this configuration optimizes thd and sfdr performance of the adc by reducing the effects of transformer parasitics. however, the source imped- ance combined with the shunt capacitance provided by a pcb and the adc? parasitic capacitance limit the adc? full-power input bandwidth to approximately 600mhz. mc100lvel16d vgnd agnd ognd d0p/n?11p/n av cc v clk 0.1 f 0.1 f 0.1 f 0.1 f 0.01 f single-ended input terminal 150 150 clkp clkn inpinn ov cc 12 2 8 45 7 6 3 50 510 510 max1215 figure 7. differential, ac-coupled, lvpecl-compatible clock input configuration downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications ______________________________________________________________________________________ 15 to further enhance thd and sfdr performance at highinput frequencies (>100mhz), a second transformer (figure 8) should be placed in series with the single- ended-to-differential conversion transformer. this trans- former reduces the increase of even-order harmonics at high frequencies. single-ended, ac-coupled analog inputs although not recommended, the max1215 can be used in single-ended mode (figure 9). analog signals can be ac-coupled to the positive input inp through a 0.1? capacitor and terminated with a 49.9 resistor to agnd. the negative input should be reverse terminated with49.9 resistors and ac-grounded with a 0.1? capacitor. grounding, bypassing, and board layout considerations the max1215 requires board layout design techniquessuitable for high-speed data converters. this adc pro- vides separate analog and digital power supplies. the analog and digital supply voltage pins accept 1.7v to 1.9v input voltage ranges. although both supply types can be combined and supplied from one source, it is recommended to use separate sources to cut down on performance degradation caused by digital switching currents, which can couple into the analog supply net- work. isolate analog and digital supplies (av cc and ov cc ) where they enter the pcb with separate net- works of ferrite beads and capacitors to their corre-sponding grounds (agnd, ognd). agnd ognd d0p/n?11p/n av cc inp inn ov cc 12 max1215 0.1 f 25 25 0.1 f adt1-1wt adt1-1wt 10 10 single-ended input terminal agnd ognd d0p/n?11p/n av cc inp 49.9 1% 49.9 1% inn ov cc 12 max1215 0.1 f single-ended input terminal 0.1 f figure 8. analog input configuration with back-to-back transformers and secondary-side termination figure 9. single-ended ac-coupled analog input configuration downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications 16 ______________________________________________________________________________________ to achieve optimum performance, provide each supply with a separate network of a 47f tantalum capacitor and parallel combinations of 10f and 1f ceramic capacitors. additionally, the adc requires each supply pin to be bypassed with separate 0.1f ceramic capacitors (figure 10). locate these capacitors directly at the adc supply pins or as close as possible to the max1215. choose surface-mount capacitors, whose preferred location should be on the same side as the converter to save space and minimize the inductance. if close placement on the same side is not possible, these bypassing capacitors may be routed through vias to the bottom side of the pcb. multilayer boards with separated ground and power planes produce the highest level of signal integrity. consider the use of a split ground plane arranged to match the physical location of analog and digital ground on the adc? package. the two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. the dynamic currents that may need to travel long distances before they are recombined at a com- mon-source ground, resulting in large and undesirable ground loops, are a major concern with this approach. ground loops can degrade the input noise by coupling back to the analog front-end of the converter, resulting in increased spurious activity, leading to decreased noise performance. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, digital systems ground. to minimize the coupling of the digital output signals from the analog input, segregate the digital output bus carefully from theanalog input circuitry. to further minimize the effects of digital noise coupling, ground return vias can be posi- tioned throughout the layout to divert digital switching currents away from the sensitive analog sections of the adc. this approach does not require split ground planes, but can be accomplished by placing substantial ground connections between the analog front-end and the digital outputs. the max1215 is packaged in a 68-pin qfn-ep pack- age (package code: g6800-4) , providing greater design flexibility, increased thermal dissipation, andoptimized ac performance of the adc. the exposed paddle (ep) must be soldered down to agnd. in this package, the data converter die is attached to an ep lead frame with the back of this frame exposed at the package bottom surface, facing the pcb side of the package. this allows a solid attachment of the package to the board with standard infrared (ir) flow soldering techniques. thermal efficiency is one of the factors for selecting a package with an exposed pad for the max1215. the exposed pad improves thermal and ensures a solid ground connection between the dac and the pcb? analog ground layer. considerable care must be taken when routing the digi- tal output traces for a high-speed, high-resolution data converter. it is recommended running the lvds output traces as differential lines with 100 matched imped- ance from the adc to the lvds load device. agnd note: each power-supply pin (analog and digital) should be decoupled with an individual 0.1 f capacitor as close as possible to the adc. bypassing?dc level bypassing?oard level analog power-supply source ognd agnd ognd d0p/n?11p/n 1 f 10 f 0.1 f 0.1 f 47 f av cc ov cc 12 max1215 av cc digital/outputdriver power- supply source 1 f 10 f4 7 f ov cc figure 10. grounding, bypassing, and decoupling recommendations for the max1215 downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications ______________________________________________________________________________________ 17 static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on anactual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. however, the static linearity parameters for the max1215 are mea- sured using the histogram method with a 10mhz input frequency. differential nonlinearity (dnl) differential nonlinearity is the difference between anactual step width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes and a monotonic transfer function. the max1215? dnl specification is measured with the his- togram method based on a 10mhz input tone. dynamic parameter definitions aperture jitter figure 11 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 11). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digitalsamples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adc? reso-lution (n bits): snr [max] = 6.02 x n + 1.76 in reality, other noise sources such as thermal noise,clock jitter, signal phase noise, and transfer function nonlinearities are also contributing to the snr calcula- tion and should be considered when determining the signal-to-noise ratio in adc. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig-nal to all spectral components excluding the fundamen- tal and the dc offset. in the case of the max1215, sinad is computed from a curve fit. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier fre-quency (maximum signal component) to the rms value of the next-largest noise or harmonic distortion compo- nent. sfdr is usually measured in dbc with respect to the carrier frequency amplitude or in dbfs with respect to the adc? full-scale range. intermodulation distortion (imd) imd is the ratio of the rms sum of the intermodulationproducts to the rms sum of the two fundamental input tones. this is expressed as: the fundamental input tone amplitudes (v 1 and v 2 ) are at -7dbfs. the intermodulation products are the amplitudesof the output spectrum at the following frequencies: second-order intermodulation products: f in1 + f in2 , f in2 - f in1 third-order intermodulation products: 2 x f in1 - f in2 , 2 x f in2 - f in1 , 2 x f in1 + f in2 , 2 x f in2 + f in1 fourth-order intermodulation products: 3 x f in1 - f in2 , 3 x f in2 - f in1 , 3 x f in1 + f in2 , 3 x f in2 + f in1 fifth-order intermodulation products: 3 x f in1 - 2 x f in2 , 3 x f in2 -2 x f in1 , 3 x f in1 +2 x f in2 , 3 x f in2 + 2 x f in1 full-power bandwidth a large -1dbfs analog input signal is applied to anadc and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. the -3db point is defined as the full-power input bandwidth frequency of the adc. imd vv v v vv im im im imn log ...... = ++++ + ?? ?? ?? ?? 20 1 2 2 2 3 22 1 2 2 2 hold analog input sampled data (t/h) t/h t ad t aj track track clkn clkp figure 11. aperture jitter/delay specifications downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications 18 ______________________________________________________________________________________ noise-power ratio (npr) npr is commonly used to characterize the return path ofcable systems where the signals are typically individual quadrature amplitude-modulated (qam) carriers with a frequency spectrum similar to noise. numerous such carriers are operated in a continuous spectrum, generat- ing a noise-like signal, which covers a relatively broad bandwidth. to test the max1215 for npr, a ?oise-like signal is passed through a high-order bandpass filter to produce an approximately square spectral pedestal of noise with about the same bandwidth as the signals being simulated. following the bandpass filter, the signal is passed through a narrow band-reject filter to produce a deep notch at the center of the noise pedestal. finally, this signal is applied to the max1215 and its digitized results analyzed. the rms noise power of the signal inside the notch is compared with the rms noise level outside the notch using an fft. note that the npr test requires sufficiently long data records to guarantee asuitable number of samples inside the notch. npr for the max1215 was determined for 50mhz noise bandwidth signals, simulating a typical cable signal environment (see the typical operating characteristics for test details and results), and with a notch frequency of 28.8mhz. pin-compatible, lower- speed/resolution versions applications that require lower resolution, a choice ofbuffered or nonbuffered inputs, and/or higher speed can refer to other family members of the max1215. adjusting an application to a lower resolution has been simplified by maintaining an identical pinout for all mem- bers of this high-speed family. see the pin-compatible versions table on the first page of this data sheet for a selection of different resolution and speed grades. pin configuration 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 av cc agnd av cc top view av cc ogndov cc orporn d11p d11n d10p d10n 52 53 d9p d9n agndagnd av cc clkn clkp av cc agnd ov cc ognd d0n ov cc d1n d0pd1p d6pd6n ognd ov cc dclkp dclknov cc d5p d5n d4p 35 36 37 d4n d3p d3n agnd inn inp agnd av cc agnd agnd av cc av cc av cc agnd refadj refio agnd 48 d7n av cc 64 agnd 65 66 67 agndagnd av cc 68 t/b 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 d2n d2p 34 33 49 50 d8nd7p ep 51 d8p 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 clkdiv 17 max1215 qfn downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications ______________________________________________________________________________________ 19 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) for the max1215 , the package code is g6800-4. downloaded from: http:///
max1215 1.8v, 12-bit, 250msps adc for broadband applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) revision history pages changed at rev 1: 1, 2, 12?6, 18, 20 downloaded from: http:///

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